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WM8281ECS/R Datenblatt(PDF) 357 Page - Cirrus Logic

Teilenummer WM8281ECS/R
Bauteilbeschribung  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
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Hersteller  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8281ECS/R Datenblatt(HTML) 357 Page - Cirrus Logic

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WM8281
Rev 4.0
357
REG
NAME
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DEFAULT
R3345 (D11h) IRQ2 Status 2
0
0
0
0
DSP4_
RAM_
RDY_
EINT2
DSP3_
RAM_
RDY_
EINT2
DSP2_
RAM_
RDY_
EINT2
DSP1_
RAM_
RDY_
EINT2
DSP_I
RQ8_E
INT2
DSP_I
RQ7_E
INT2
DSP_I
RQ6_E
INT2
DSP_I
RQ5_E
INT2
DSP_I
RQ4_E
INT2
DSP_I
RQ3_E
INT2
DSP_I
RQ2_E
INT2
DSP_I
RQ1_E
INT2
0000h
R3346 (D12h) IRQ2 Status 3
SPK_
OVER
HEAT_
WARN
_EINT
2
SPK_
OVER
HEAT_
EINT2
HPDE
T_EIN
T2
MICDE
T_EIN
T2
WSEQ
_DON
E_EIN
T2
DRC2_
SIG_D
ET_EI
NT2
DRC1_
SIG_D
ET_EI
NT2
ASRC
2_LOC
K_EIN
T2
ASRC
1_LOC
K_EIN
T2
UNDE
RCLO
CKED
_EINT
2
OVER
CLOC
KED_E
INT2
0
FLL2_
LOCK_
EINT2
FLL1_
LOCK_
EINT2
CLKG
EN_E
RR_EI
NT2
CLKG
EN_E
RR_A
SYNC
_EINT
2
0000h
R3347 (D13h) IRQ2 Status 4
0
0
0
CTRLI
F_ERR
_EINT
2
MIXER
_DRO
PPED_
SAMP
LE_EI
NT2
ASYN
C_CLK
_ENA_
LOW_
EINT2
SYSCL
K_ENA
_LOW
_EINT
2
ISRC1
_CFG_
ERR_
EINT2
ISRC2
_CFG_
ERR_
EINT2
ISRC3
_CFG_
ERR_
EINT2
HP3R_
DONE
_EINT
HP3L_
DONE
_EINT
2
HP2R_
DONE
_EINT
2
HP2L_
DONE
_EINT
2
HP1R_
DONE
_EINT
2
HP1L_
DONE
_EINT
2
0000h
R3348 (D14h) IRQ2 Status 5
0
0
0
0
0
0
0
BOOT
_DON
E_EIN
T2
0
0
ADC_
OVER
FLOW
_EINT
2
ADC_F
IFO_O
U_EIN
T2
ASRC
_CFG_
ERR_
EINT2
0
FLL2_
CLOC
K_OK_
EINT2
FLL1_
CLOC
K_OK_
EINT2
0000h
R3349 (D15h) IRQ2 Status 6
DSP_S
HARE
D_WR
_COLL
_EINT
2
SPK_S
HUTD
OWN_
EINT2
SPKO
UTR_S
HORT
_EINT
2
SPKO
UTL_S
HORT
_EINT
2
HP3R_
SC_N
EG_EI
NT2
HP3R_
SC_P
OS_EI
NT2
HP3L_
SC_N
EG_EI
NT2
HP3L_
SC_P
OS_EI
NT2
HP2R_
SC_N
EG_EI
NT2
HP2R_
SC_P
OS_EI
NT2
HP2L_
SC_N
EG_EI
NT2
HP2L_
SC_P
OS_EI
NT2
HP1R_
SC_N
EG_EI
NT2
HP1R_
SC_P
OS_EI
NT2
HP1L_
SC_N
EG_EI
NT2
HP1L_
SC_P
OS_EI
NT2
0000h
R3352 (D18h) IRQ2 Status 1
Mask
0
0
0
0
0
0
0
0
0
0
0
0
IM_GP
4_EIN
T2
IM_GP
3_EIN
T2
IM_GP
2_EIN
T2
IM_GP
1_EIN
T2
000Fh
R3353 (D19h) IRQ2 Status 2
Mask
0
0
0
0
IM_DS
P4_RA
M_RD
Y_EIN
T2
IM_DS
P3_RA
M_RD
Y_EIN
T2
IM_DS
P2_RA
M_RD
Y_EIN
T2
IM_DS
P1_RA
M_RD
Y_EIN
T2
IM_DS
P_IRQ
8_EIN
T2
IM_DS
P_IRQ
7_EIN
T2
IM_DS
P_IRQ
6_EIN
T2
IM_DS
P_IRQ
5_EIN
T2
IM_DS
P_IRQ
4_EIN
T2
IM_DS
P_IRQ
3_EIN
T2
IM_DS
P_IRQ
2_EIN
T2
IM_DS
P_IRQ
1_EIN
T2
0FFFh
R3354
(D1Ah)
IRQ2 Status 3
Mask
IM_SP
K_OV
ERHE
AT_W
ARN_
EINT2
IM_SP
K_OV
ERHE
AT_EI
NT2
IM_HP
DET_E
INT2
IM_MI
CDET_
EINT2
IM_WS
EQ_D
ONE_
EINT2
IM_DR
C2_SI
G_DE
T_EIN
T2
IM_DR
C1_SI
G_DE
T_EIN
T2
IM_AS
RC2_L
OCK_
EINT2
IM_AS
RC1_L
OCK_
EINT2
IM_UN
DERC
LOCK
ED_EI
NT2
IM_OV
ERCL
OCKE
D_EIN
T2
0
IM_FL
L2_LO
CK_EI
NT2
IM_FL
L1_LO
CK_EI
NT2
IM_CL
KGEN
_ERR_
EINT2
IM_CL
KGEN
_ERR_
ASYN
C_EIN
T2
FFEFh
R3355
(D1Bh)
IRQ2 Status 4
Mask
1
1
1
IM_CT
RLIF_
ERR_
EINT2
IM_MI
XER_
DROP
PED_S
AMPL
E_EIN
T2
IM_AS
YNC_
CLK_E
NA_LO
W_EIN
T2
IM_SY
SCLK_
ENA_L
OW_EI
NT2
IM_IS
RC1_C
FG_E
RR_EI
NT2
IM_IS
RC2_C
FG_E
RR_EI
NT2
IM_IS
RC3_C
FG_E
RR_EI
NT2
IM_HP
3R_D
ONE_
EINT
IM_HP
3L_DO
NE_EI
NT2
IM_HP
2R_D
ONE_
EINT2
IM_HP
2L_DO
NE_EI
NT2
IM_HP
1R_D
ONE_
EINT2
IM_HP
1L_DO
NE_EI
NT2
FFFFh
R3356
(D1Ch)
IRQ2 Status 5
Mask
1
1
1
1
1
1
1
IM_BO
OT_D
ONE_
EINT2
0
0
IM_AD
C_OV
ERFL
OW_EI
NT2
IM_AD
C_FIF
O_OU
_EINT
2
IM_AS
RC_C
FG_E
RR_EI
NT2
0
IM_FL
L2_CL
OCK_
OK_EI
NT2
IM_FL
L1_CL
OCK_
OK_EI
NT2
FE3Bh
R3357
(D1Dh)
IRQ2 Status 6
Mask
IM_DS
P_SHA
RED_
WR_C
OLL_E
INT2
IM_SP
K_SH
UTDO
WN_EI
NT2
IM_SP
KOUT
R_SH
ORT_
EINT2
IM_SP
KOUT
L_SHO
RT_EI
NT2
IM_HP
3R_SC
_NEG_
EINT2
IM_HP
3R_SC
_POS_
EINT2
IM_HP
3L_SC
_NEG_
EINT2
IM_HP
3L_SC
_POS_
EINT2
IM_HP
2R_SC
_NEG_
EINT2
IM_HP
2R_SC
_POS_
EINT2
IM_HP
2L_SC
_NEG_
EINT2
IM_HP
2L_SC
_POS_
EINT2
IM_HP
1R_SC
_NEG_
EINT2
IM_HP
1R_SC
_POS_
EINT2
IM_HP
1L_SC
_NEG_
EINT2
IM_HP
1L_SC
_POS_
EINT2
FFFFh
R3359
(D1Fh)
IRQ2 Control
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IM_IR
Q2
0000h



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