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STM32L476RG Datenblatt(PDF) 176 Page - STMicroelectronics

Teilenummer STM32L476RG
Bauteilbeschribung  Ultra-low-power ARM® Cortex®-M4 32-bit MCUFPU, 100DMIPS, up to 1MB Flash, 128 KB SRAM, USB OTG FS, LCD, analog, audio
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Hersteller  STMICROELECTRONICS [STMicroelectronics]
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STM32L476RG Datenblatt(HTML) 176 Page - STMicroelectronics

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Electrical characteristics
STM32L476xx
176/232
DocID025976 Rev 4
6.3.25
DFSDM characteristics
Unless otherwise specified, the parameters given in Table 78 for DFSDM are derived from
tests performed under the ambient temperature, fAPB2 frequency and VDD supply voltage
conditions summarized in Table 22: General operating conditions.
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5 ₓ VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDM_CKINy, DFSDM_DATINy, DFSDM_CKOUT for DFSDM).
Table 78. DFSDM characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fDFSDMCLK DFSDM clock
-
-
-
fSYSCLK
MHz
fCKIN
(1/TCKIN)
Input clock
frequency
SPI mode (SITP[1:0] = 01)
-
-
20
(fDFSDMCLK/4)
fCKOUT
Output clock
frequency
--
-
20
MHz
DuCyCKOUT
Output clock
frequency
duty cycle
-45
50
55
%
twh(CKIN)
twl(CKIN)
Input clock
high and low
time
SPI mode (SITP[1:0] = 01),
External clock mode
(SPICKSEL[1:0] = 0)
TCKIN/2-0.5 TCKIN/2
-
ns
tsu
Data input
setup time
SPI mode (SITP[1:0]=01),
External clock mode
(SPICKSEL[1:0] = 0)
0-
-
th
Data input
hold time
SPI mode (SITP[1:0]=01),
External clock mode
(SPICKSEL[1:0] = 0)
2-
-
TManchester
Manchester
data period
(recovered
clock period)
Manchester mode (SITP[1:0]
= 10 or 11),
Internal clock mode
(SPICKSEL[1:0]
≠ 0)
(CKOUT
DIV+1)
ₓ
TDFSDMCLK
-
(2
ₓ CKOUTDIV)
ₓ TDFSDMCLK
1. Data based on characterization results, not tested in production.



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