LATCH
AI

A **Latch** is a non-clocked (asynchronous) electronic circuit used to store a single bit of binary information (0 or a 1). It is the fundamental building block of sequential logic systems and computer memory.
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## 1. Core Concept
Unlike a **Flip-Flop**, which is "edge-triggered" (changes state only at the moment a clock pulses), a **Latch** is "level-triggered." This means it responds to the input signal as long as the "Enable" pin is active.
### Key Characteristics:
* **Bistable:** It has two stable states (High/Low).
* **Feedback Loop:** It uses its output as an input to maintain its state.
* **Memory:** It "remembers" the last input even after the signal is removed (provided power is maintained).
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## 2. Common Types of Latches
| Latch Type | Inputs | Description |
| :--- | :--- | :--- |
| **SR Latch** | Set (S), Reset (R) | The simplest form. Setting S makes output 1; setting R makes it 0. |
| **Gated SR Latch** | S, R, Enable (E) | Only changes state when the Enable signal is High. |
| **D Latch** | Data (D), Enable (E) | Eliminates the "invalid state" of SR latches; output follows D when E is high. |
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## 3. The SR Latch (Set-Reset)
The most basic latch can be constructed using two cross-coupled **NOR** gates or **NAND** gates.
### Truth Table (NOR Implementation)
| S | R | Q (Output) | State |
| :--- | :--- | :--- | :--- |
| 0 | 0 | Last Value | Hold (No change) |
| 1 | 0 | 1 | Set |
| 0 | 1 | 0 | Reset |
| 1 | 1 | ? | **Invalid/Forbidden** |
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## 4. Latch vs. Flip-Flop
It is vital to distinguish between these two components in digital electronics:
| Feature | Latch | Flip-Flop |
| :--- | :--- | :--- |
| **Triggering** | Level Triggered (High or Low) | Edge Triggered (Rising or Falling) |
| **Timing** | Asynchronous (mostly) | Synchronous (with Clock) |
| **Complexity** | Simpler/Smaller | More complex (uses multiple latches) |
| **Use Case** | Data buffering, simple storage | Microprocessors, complex registers |
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## 5. Applications
1. **Switch Debouncing:** Used to prevent a single mechanical switch press from being read as multiple "bounces" by a microprocessor.
2. **Data Storage:** Acting as basic 1-bit memory cells.
3. **IO Ports:** Holding data for peripheral devices so the CPU can move to other tasks.
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- ⤷
What is the 'invalid state' in an SR Latch and why does it occur?
- ⤷ How do you convert a Latch into a Flip-Flop?
- ⤷ Can you explain the circuit diagram of a D Latch?