Functional Description[1]
The CY7C1345F is a 131,072 x 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Features
• 128K × 36 common I/O
• 3.3V –5% and +10% core power supply (VDD)
• 2.5V or 3.3V I/O supply (VDDQ)
• Fast clock-to-output times
   — 6.5 ns (133-MHz version)
   — 7.5 ns (117-MHz version)
   — 8.0 ns (100-MHz version)
   — 11.0 ns (66-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable • Offered in JEDEC-standard 100-pin TQFP and 119-ball BGA packages
• “ZZ” Sleep Mode option