Description
The TC551001APL is a 1,048,576 bit CMOS static random access memory organized as 131,072 words by 8 bits and operated
from a single 5V power supply. Advanced circuit techniques provide both high speed and low power features with an operating cur-
rent of 5mA/MHz (typ.) and a minimum cycle time of 70ns. When CE1 is a logical high, or CE2 is low, the device is placed in a low
power standby mode in which the standby current is 2μA typically. The TC551001APL has three control inputs. Chip enable inputs
(CE1, CE2) allow for device selection and data retention control, while an output enable input (OE) provides fast memory access.
The TC551001APL is suitable for use in microprocessor systems where high speed, low power, and battery backup are required.
The TC551001APL-L(LV) operates and is characterized at both 3 and 5 volts.
The TC551001APL is offered in a standard dual-in-line 32-pin plastic package, a small outline plastic package, and a thin small
outline plastic package (forward type, reverse type).

Features
• Low power dissipation:
• Standby current:
Single 5V power supply
• Access time (max.)
Access Time
CE1 Access Time
CE2 Access Time
OE Access Time
27.5mW/MHz (typ.)
4uA (max.) at Ta = 25°C
TC551001APL/AFL/AFTL/ATRL
-70L(LV) -85L(LV) -10L(LV)
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
35ns
45ns
50ns
CE1, CE2
Power down feature:
Data retention supply voltage:
Inputs and outputs TTL compatible
• Package
TC551001APL
TC551001AFL
TC551001AFTL
TC551001ATRL
2.0 - 5.5V
F
: DIP32-P-600
: SOP32-P-525
: TSOP32-P-0820
: TSOP32-P-0820A