FEATURES:
• Guaranteed Low Skew < 60ps (max)
• Very low duty cycle distortion
• High speed propagation delay < 2.5ns. (max)
• Up to 250MHz operation
• Very low CMOS power levels
• 1.5V VDDQ for HSTL interface
• Hot insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input
interface
• Selectable differential or single-ended inputs and fi ve single-ended outputs
• 2.5V VDD
• Available in TSSOP package
• For new designs use functional replacement 8L30110

DESCRIPTION:
The 5T905 2.5V single data rate (SDR) clock buffer is a user-selectable
single-ended or differential input to fi ve single-ended outputs buffer built on
advanced metal CMOS technology. The SDR clock buffer fanout from a
single or differential input to fi ve single-ended outputs reduces the loading
on the preceding driver and provides an effi cient clock distribution network.
The IDT5T905 can act as a translator from a differential HSTL, eHSTL,
1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to
HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled
by 3-level input signals that may be hard-wired to appropriate high-mid-low
levels. Multiple power and grounds reduce noise.