General Description
• Up to 30 MIPS operation at 60MHz core frequency
• Up to 40 MIPS operation at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
• Hardware DO and REP loops
• 6-channel PWM Module with fault input

1.1 56F802 Features
1.1.1Processing Core
•Efficient 16-bit 56800 family controller engine with dual Harvard architecture
•As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency
•Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
•Two 36-bit accumulators including extension bits
•16-bit bidirectional barrel shifter
•Parallel instruction set with unique processor addressing modes
•Hardware DO and REP loops
•Three internal address buses and one external address bus
•Four internal data buses and one external data bus
•Instruction set supports both DSP and controller functions
•Controller style addressing modes and instructions for compact code
•Efficient C compiler and local variable support
•Software subroutine and interrupt stack with depth limited only by memory
•JTAG/OnCE debug programming interface
• Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel)
• Serial Communications Interface (SCI)
• Two General Purpose Quad Timers with 2 external
outputs
• 8K × 16-bit words (16KB) Program Flash
• 1K × 16-bit words (2KB) Program RAM
• 2K × 16-bit words (4KB) Data Flash
• 1K × 16-bit words (2KB) Data RAM
• 2K × 16-bit words (4KB) Boot Flash
• JTAG/OnCETM port for debugging
• On-chip relaxation oscillator
• 4 shared GPIO
• 32-pin LQFP Package

1.1.2Memory
•Harvard architecture permits as many as three simultaneous accesses to program and data memory
•On-chip memory including a low-cost, high-volume Flash solution
—8K × 16 bit words of Program Flash
—1K × 16-bit words of Program RAM
—2K × 16-bit words of Data Flash
—1K × 16-bit words of Data RAM
—2K × 16-bit words of Boot Flash
•Programmable Boot Flash supports customized boot code and field upgrades of stored code through a variety of interfaces (JTAG)

1.1.3Peripheral Circuits for 56F802
•Pulse Width Modulator (PWM) with six PWM outputs with deadtime insertion and fault protection; supports both center- and edge-aligned modes
•Two 12-bit, Analog-to-Digital Converters (ADCs), 1 x 2 channel and 1 x 3 channel, which support two simultaneous conversions; ADC and PWM modules can be synchronized
•Two General Purpose Quad Timers with two external pins (or two GPIO)
•Serial Communication Interface (SCI) with two pins (or two GPIO)
•Four multiplexed General Purpose I/O (GPIO) pins
•Computer-Operating Properly (COP) watchdog timer
•External interrupts via GPIO
•Trimmable on-chip relaxation oscillator
•External reset pin for hardware reset
•JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
•Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock

1.1.4Energy Information
•Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
•Uses a single 3.3V power supply
•On-chip regulators for digital and analog circuitry to lower cost and reduce noise
•Wait and Stop modes available
•Integrated power supervisor