FEATURES
Digital Signal Processing Core
• Efficient, object code compatible with the 24-bit DSP56000 core engine
• Up to 40.5 Million Instructions Per Second (MIPS)—24.7 ns instruction cycle at
81 MHz; up to 324 Million Operations Per Second (MOPS) at 81 MHz
• Highly parallel instruction set with unique DSP addressing modes
• Two 56-bit accumulators including extension byte
• Parallel 24x24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
• Double precision 48x48-bit multiply with 96-bit result in 6 instruction cycles
• 56-bit addition/subtraction in 1 instruction cycle
• Fractional and integer arithmetic with support for multiprecision arithmetic
• Hardware support for block floating-point Fast Fourier Transforms (FFT)
• Hardware nested DO loops
• Zero-overhead fast interrupts (2 instruction cycles)
• Four 24-bit internal data buses and three 16-bit internal address buses for
simultaneous accesses to one program and two data memories
• Fabricated in high-density CMOS