FEATURES
• Single-Chip Microcontroller
• RISC MCU Central Processing Unit (RCPU)
— 32-Bit PowerPC Architecture
— Single-Issue Processor
— Integrated Floating-Point Unit
— Branch Prediction for Prefetch
— Branch Folding
— 32 x 32 Bits General-Purpose Register File
— 32 x 64 Bits Floating-Point Register File
— Precise Exception Model
— Internal Harvard Architecture: Load/Store Bus (L-Bus), Instruction Bus (I-Bus)
• System Interface Unit (SIU)
— Chip-Select Logic to Reduce or Eliminate External Decoding Logic
— Supports a Variety of Memory Types (SRAM, EEPROM)
— Supports 16- and 32-bit Devices
— System Protection Features Including Bus Monitor, Decrementer, and Periodic Interrupt
Timer
— On-Chip Phase-Locked Loop (PLL)
— Five Dual-Purpose I/O Ports, Two Dual-Purpose Output Ports
• Peripheral Control Unit (PCU)
— Software Watchdog
— Interrupt Controller to Manage External and Internal Interrupts to the CPU
— Dual-Purpose I/O Port
— L-bus IMB Interface (LIMB) Connecting L-Bus to Intermodule Bus 2 (IMB2)
• Development Support
— Internal Breakpoints
— External Watchpoints
— Internal Bus Visibility
— Program Flow Tracking
— Development Port
• 4-Kbyte On-Chip Instruction Cache (I-Cache)
• 4-Kbyte On-Chip Static RAM (SRAM)
• 3.3-V Supply Voltage
• Frequency: dc to 25 MHz (40 MHz in Future Versions)
• Power Consumption: 530 mW @ 25 MHz
• Interrupt Response Time: Less than 1 µs @ 25 MHz