Description
The ICS552-01 produces 8 low-skew copies of the
multiple input clock or fundamental, parallel-mode
crystal. Unlike other clock drivers, these parts do not
require a separate oscillator for the input. Using IDT’s
patented Phase-Locked Loop (PLL) to multiply the input
frequency, it is ideal for generating and distributing
multiple high-frequency clocks. This is a single chip
used for 3 different applications:
1) ICS552-01 (A mode) — an Oscillator mutiplier
2) ICS552-01 (B mode) — a Dual 1:4 buffer
3) ICS552-01 (C mode) — a 1:8 Oscillator buffer
Features (all)
• Packaged as 20-pin SSOP (QSOP)
• Pb-free packaging
• Operating voltages of 3.0 V to 5.5 V
• Industrial temperature available
Features (specific)
ICS552-01 (for A mode)
• Contains on-chip multiplier with selections of x1,
x1.33, x2, x2.66, x3, x3.33, x4, x4.66, x5, and x6
Block Diagram (ICS552-01—A mode)
• Power-down and Tri-state modes
ICS552-01 (for B mode)
• Up to 200 MHz clock input/output at 3.3 V
• Low skew of 250 ps maximum for any bank of four
• Inputs can be connected together for a 1 to 8 buffer
with 250 ps skew between any outputs
• Non-inverting buffer mode
• Ideal for clock networks
• Output Enable mode tri-states outputs
• Full CMOS output swing with 25 mA output drive
capability at TTL levels
• Advanced, low power, sub-micron CMOS process
ICS552-01 (for C mode)
• Use with 25 MHz crystal for networking
• Use with 27 MHz crystal for MPEG
ICS552-01 (for A and C modes)
• Input frequency of 10.0 to 27.0 MHz
• Provides 8 low-skew outputs (<250 ps)
• Output clock duty cycle of 40/60 at 3.3 V