3.3 V / 5 V ECL 9−Bit Shift Register

The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel input data, while S−IN accepts serial input data. The QT0:87 outputs do not need to be terminated for the shift operation to function. To minimize power, any Q output not used should be left unterminated.

Features
• Shift Frequency >2.8 GHz (Typical)
• 9-Bit for Byte−Parity Applications
• Asynchronous Master Reset
• Dual Clocks
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Pb−Free Packages are Available