1. General description
The 74LVC1G18 is a 1-to-2 demultiplexer with 3-state outputs. The device buffers the data on input
A and passes it to output 1Y or 2Y, depending on whether the state of the select input (S) is LOW
or HIGH. The unused output assumes the high impedence OFF-state. Inputs can be driven from
either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed
3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry
disables the output, preventing the potentially damaging backflow current through the device when
it is powered down.
2. Features and benefits
• Wide supply voltage range from 1.65 V to 5.5 V
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power dissipation
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• IOFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
• ESD protection:
• HBM EIA/JESD22-A114E exceeds 2000 V
• MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from -40 to +85 °C and -40 to +125 °C.