FEATURES
• Provides a 25.6-Mbps ATM PHY (PMD & TC) function for six circuits
• Conforms to the ATM Forum PHY interface specifications (af-phy-0040.000 November 1995).
• UTOPIA Level 2 V1.0 (af-phy-0039.000 June 1995: max. 8 bits/40 MHz) interface
• Three-cell built-in transmit/receive FIFOs for each circuit
• PMD sublayer functions:
(a) Built-in clock recovery.
(b) Built-in equalizer.
• TC sublayer functions:
(a) NRZI encoder/decoder.
(b) Command byte insertion/detection.
(c) 4B/5B encoder/decoder.
(d) Cell scrambler/descrambler.
(e) HEC generation/verification.
• CPU interface: Intel or Motorola can be selected.
• Supports STP and UTP (Categories 3, 4, 5).
• Loopback function: Loopback in the PMD and ATM layers.
• Operation And Maintenance (OAM) functions: Input failure detection, HEC error detection and 4B/5B code error detection.
• Test function: Supports JTAG.
• Power supply voltage: 3.3 V ± 5 %.