Features
Lowest Cost Solution for high quality
multimedia networking
• Data rate of over 24.5 Mbit/s
⇒ Bandwidth allocable for both asynchronous and
synchronous data
⇒ Independent 768 kbit/s control channel
• Designed for ultra-low cost network nodes
⇒ On-chip support of fiber optic physical layer
⇒ Stand-alone operation (no MCU) by remote
access
⇒ No buffering required for audio applications
On-chip Network Management Functions
• Automatic multimedia channel allocation
• Automatic wake-up on sensing network activity
• Node position and delay detection
• Fail-safe node bypass and error reporting
Flexible I/O
• Consumer Electronic / Multimedia I/O
⇒ Multiple speed CD & Media player interfaces
⇒ Real-time I/O with various data formats
⇒ 1-8x speed IEC 958 (S/PDIF or AES-EBU) port
⇒ Transparent channel with sample rate up to
3 MHz
• Control I/O
⇒ High speed IIC/SPI serial control interface
⇒ FIFO buffered 8-bit parallel control interface
⇒ Transparent interface up to 128 kbit/s.
Easy System Integration
• Low power and zero power mode
• Low power 5 V operation
• 44-pin TQFP package

Description
The OS8104 is a highly integrated CMOS Transceiver
IC with full support for the 24.5 Mbit/s MOST Multimedia and Control network.
This high performance, low cost, real-time network
utilizes a ring topology and a plastic optical fiber (POF)
physical layer, both of which are supported directly by
the OS8104.
All relevant network management functions are
handled on-chip. An ultra-low jitter PLL guarantees
high quality audio and video transmission, and clock
recovery over a wide frequency range.
The 24.5 Mbit/s aggregate bit rate provides the
capability to network up to 60 byte-wide synchronous
data channels (equivalent to 15 stereo, CD-audio
channels) or any appropriate combination of synchronous and asynchronous data streams. Control data
is also networked, transparently to the source data
channels, at an aggregate bit rate of 768 kbits/s.
The OS8104 can be managed remotely, from any
other network node; or locally via the Control Port in
I
2
C or SPI more, or through a parallel format.
Programmable serial and parallel real-time data
interfaces, with different clock and data modes,
support connections to multiple speed CD drives and
other consumer electronic devices, as well as comple–
mentary ICs such as A/D and D/A converters or DSPs.

2 General Overview
2.1 Functional Description
The OS8104 chip contains a RISC microcontroller-based MOST Routing Engine and several peripherals
including a clock manager, Source Data Ports, wake-up logic and an I2
C/SPI/parallel Control Port.
SDA
SCL
[AD0,SDIN]
[AD1, /CS]
MOST
Routing
Engine
Source
Data
Ports
Clock
Manager
I2C/SPI
Port
SX0..3,D4..7
SR0..3,D0..3
XTI
XTO
TX
RX
Network
Interface
Wake-up
Logic
&
Power
Management
Figure 2-1: MOST Routing Engine
The network interface includes an ultra-low jitter Phase Lock Loop (PLL) and a channel demodulator on
the input side (RX). The network output (TX) provides a channel-coded signal. Those signals can be
connected directly to optical receiving/transmitting devices (FOT units) or balanced line drivers. The line
quality can be monitored using the built-in error detection circuit.
Each device can generate the network clock or synchronize to it; however, only one device can generate
the clock and the frame structure for a particular network. Various A/D converters, D/A converters, digital
signal processors, and Media Players (CD-AUDIO/VIDEO/ROM etc.) can be synchronized through one of
the many clock and serial interface modes.
The Source Data Ports provide a synchronous data interface to the network, generally used for
multimedia devices. Data sources and sinks can be connected to the Source Ports to transfer data to
another node on the network, or receive data from another node on the network. The Source Ports
support up to four simultaneous inputs and four simultaneous outputs for transferring real-time data
between external peripherals and the MOST network.