1 Features
• Vendor item drawing available, VID
V62/25633-01XE
• Radiation - Total Ionizing Dose (TID):
– TID characterized up to 50krad(Si)
– TID performance assurance up to 30krad(Si)
– Radiation Lot Acceptance Testing (RLAT) for
every wafer lot up to 30krad(Si)
• Radiation - Single-Event Effects (SEE):
– Single Event Latch-Up (SEL) immune up to
50MeV-cm2/mg at 125°C
– Single Event Transient (SET) characterized up
to LET = 50MeV-cm2/mg
• Wide operating range of 1.2V to 5.5V
• Single-supply voltage translator:
– Up translation:
• 1.2V to 1.8V
• 1.5V to 2.5V
• 1.8V to 3.3V
• 3.3V to 5.0V
– Down translation:
• 5.0V, 3.3V, 2.5V to 1.8V
• 5.0V, 3.3V to 2.5V
• 5.0V to 3.3V
• 5.5V tolerant input pins
• Supports standard pinouts
• Up to 150Mbps with 5V or 3.3V VCC
• Latch-up performance exceeds 250mA per JESD
17
• Space enhanced plastic:
– Supports defense and aerospace applications
– Controlled baseline
– Au bondwire and NiPdAu lead finish
– Meets NASA ASTM E595 outgassing
specification
– One fabrication, assembly, and test site
– Extended product life cycle
– Product traceability

2 Applications
• Enable or disable a digital signal
• Controlling an indicator LED
• Translation between communication modules and
system controllers

3 Description
The SN54SC8T9541-SEP contains eight buffers with
3-state outputs and Schmitt-Trigger inputs. The active
low output enable pins (OE1 and OE2) control all
eight channels, and are configured so that both must
be low for the outputs to be active. When the outputs
are enabled, the outputs are actively driven low or
high. When the outputs are disabled, the outputs are
set into the high-impedance state. The output level is
referenced to the supply voltage (VCC) and supports
1.8V, 2.5V, 3.3V, and 5V CMOS levels.
The input is designed with a lower threshold circuit to
support up translation for lower voltage CMOS inputs
(for example, 1.2V input to 1.8V output or 1.8V input
to 3.3V output). In addition, the 5V tolerant input pins
enable down translation (for example, 3.3V to 2.5V
output).