Key Features
▪ Complies with DECT EN 300 175-2,3,8, DECT
6.0, Japanese DECT, and Korean DECT
(1.7 GHz)
▪ Processing power
• 165.888 MHz 32-bit Arm® Cortex®-M0
• 290.304 MHz 32-bit Tensilica LX4/HiFi-3 DSP
• Triple Stereo Hardware Sample Rate
Converter (SRC) supporting 2xPCM, SPDIF, and 6xPDM
• DIP-V2 with DSAA1/2, DSC1/2, AES256, FEC
• Crypto engine supporting AES128/256, ECB
with CBC and CTR modes and HASH-256,
Random Number Generator FIPS140-2 compliant
• 4-ch SYS-DMA, 12-ch DSP-DMA controllers
▪ Development/Debug support
• Arm 2-wire SWD with 8 hardware breakpoints
and 2 watch points
• Arm instruction, DIP and DSP event trace
• DSP debugger with 1 and 5-wire JTAG interfaces
▪ Memories
• Arm Cortex-M0 16 kB instruction/data cache
• 64 kB state retainable shared System RAM
• 256 kB multibank shared DSP-RAM
• 64 B factory programmed OTP with device unique number
▪ Power management
• 1.9 V to 5 V Battery voltage, 1.2 V Core voltage
• On-chip LDOs, 1.8 V, 3.3 V, 1.2 V
• On-chip LDO 1.4 V to prevent battery wear