FEATURES
· Two Line Receivers and Eight ('109) or
Sixteen ('117) Line Drivers Meet or Exceed the
Requirements of ANSI EIA/TIA-644 Standard
· Typical Data Signaling Rates to 400 Mbps or
Clock Frequencies to 400 MHz
· Outputs Arranged in Pairs From Each Bank
· Enabling Logic Allows Individual Control of
Each Driver Output Pair, Plus All Outputs
· Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a 100-W
Load
· Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Termination Networks
· Propagation Delay Times < 4.5 ns
· Output Skew Less Than 550 ps Bank Skew
Less Than150 ps Part-to-Part Skew Less Than
1.5 ns
· Total Power Dissipation Typically <500 mW
With All Ports Enabled and at 200 MHz
· Driver Outputs or Receiver Input Equals High
Impedance When Disabled or With VCC < 1.5 V
· Bus-Pin ESD Protection Exceeds 12 kV
· Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch

DESCRIPTION
The SN65LVDS109 and SN65LVDS117 are configured
as two identical banks, each bank having one
differential line receiver connected to either four
('109) or eight ('117) differential line drivers. The
outputs are arranged in pairs having one output from
each of the two banks. Individual output enables are
provided for each pair of outputs and an additional
enable is provided for all outputs.
The line receivers and line drivers implement the
electrical characteristics of low-voltage differential
signaling (LVDS). LVDS, as specified in EIA/TIA-644,
is a data signaling technique that offers low power,
low noise emission, high noise immunity, and high
switching speeds. (Note: The ultimate rate and distance
of data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling
to the environment, and other system characteristics.)
The intended application of these devices, and the
LVDS signaling technique, is for point-to-point or
point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of
approximately 100 W. The transmission media may
be printed-circuit board traces, backplanes, or cables.
The large number of drivers integrated into the same
silicon substrate, along with the low pulse skew of
balanced signaling, provides extremely precise timing
alignment of the signals being repeated from the
inputs. This is particularly advantageous for im-
plementing system clock and data distribution trees.
The SN65LVDS109 and SN65LVDS117 are
characterized for operation from –40°C to 85°C.