1 Features
1• 2:12 Differential Buffer
• Low Additive Jitter: < 300-fs RMS in
10-kHz to 20-MHz
• Low Output Skew of 35 ps (Maximum)
• Universal Inputs Accept LVDS, LVPECL, and
LVCMOS
• Selectable Clock Inputs Through Control Pin
• 12 LVDS Outputs, ANSI EIA/TIA-644A Standard
Compatible
• Clock Frequency: Up to 800 MHz
• Device Power Supply: 2.375 V to 2.625 V
• LVDS Reference Voltage, VAC_REF, Available for
Capacitive Coupled Inputs
• Industrial Temperature Range: –40°C to 85°C
• Packaged in 6-mm × 6-mm, 40-Pin VQFN (RHA)
• ESD Protection Exceeds 3-kV HBM, 1-kV CDM

2 Applications
• Telecommunications and Networking
• Medical Imaging
• Test and Measurement Equipment
• Wireless Communications
• General-Purpose Clocking

3 Description
The CDCLVD1212 clock buffer distributes one of two
selectable clock inputs (IN0 and IN1) to 12 pairs of
differential LVDS clock outputs (OUT0 through
OUT11) with minimum skew for clock distribution.
The CDCLVD1212 can accept two clock sources into
an input multiplexer. The inputs can either be LVDS,
LVPECL, or LVCMOS.
The CDCLVD1212 is specifically designed for driving
50-Ω transmission lines. In case of driving the inputs
in single-ended mode, the appropriate bias voltage,
VAC_REF, must be applied to the unused negative
input pin.
The IN_SEL pin selects the input which is routed to
the outputs. If this pin is left open, it disables the
outputs (static). The part supports a fail-safe function.
The device incorporates an input hysteresis which
prevents random oscillation of the outputs in the
absence of an input signal.
The device operates in 2.5-V supply environment and
is characterized from –40°C to 85°C (ambient
temperature). The CDCLVD1212 is packaged in
small, 40-pin, 6-mm × 6-mm VQFN package.