1.1 Features
The i.MX RT1160 processors are based on Arm Cortex®-M7 Core™ Platform, which has the following
features:
• The Arm Cortex-M7 Core Platform:
— 32 KB L1 Instruction Cache and 32 KB L1 Data Cache
— Floating Point Unit (FPU) with single-precision and double-precision support of Armv7-M
Architecture FPv5
— Support the Arm®v7-M Thumb instruction set, defined in the Armv7-M architecture
— Integrated Memory Protection Unit (MPU), up to 16 individual protection regions
— Up to 512 KB I-TCM and D-TCM in total
— Frequency of 500 MHz
— ECC support for both cache and TCM
— Frequency of the core, as per Table 11, "Operating ranges," on page 27.
• The Arm Cortex®-M4 Core platform:
— Cortex-M4 processor with single-precision FPU defined by Armv7-M architecture FPv4-SP
— Integrated MPU with 8 individual protection regions
— 16 KB Instruction Cache, 16 KB Data Cache, and 256 KB TCM
— Frequency of 240 MHz
— ECC support for TCM and parity check support for cache
The SoC-level memory system consists of the following additional components:
— Boot ROM (256 KB)
— On-chip RAM (1 MB in total)
– Configurable 512 KB RAM shared with M7 TCM
– 256 KB RAM shared with M4 TCM
– Dedicated 256 KB OCRAM
— Secure always-on RAM (4 KB)
• External memory interfaces:
— 8/16/32-bit SDRAM, up to SDRAM-133/SDRAM-166/SDRAM-200
— 8/16-bit SLC NAND FLASH
— SD/eMMC
— SPI NOR/NAND FLASH
— Parallel NOR FLASH with XIP support
— Single/Dual channel Quad SPI FLASH with XIP support
— Hyper RAM/FLASH
— OCT FLASH
— Synchronization mode for all devices
• Timers and PWMs:
— Six General Programmable Timer (GPT) modules
– 4-channel generic 32-bit resolution timer for each
– Each supports standard capture and compare operation
— Two Periodical Interrupt Timer (PIT) modules
– Four timers for each module
– Generic 32-bit resolution timer
– Periodical interrupt generation
— Four Quad Timer (QTimer) modules
– 4-channel generic 16-bit resolution timer for each
– Each supports standard capture and compare operation
– Quadrature decoder integrated
— Four FlexPWMs
– Up to 8 individual PWM channels for each
– 16-bit resolution PWM suitable for Motor Control applications
— Four Quadrature Decoders
— Four Watch Dog (WDOG) modules
Each i.MX RT1160 processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
• Display Interface:
— Parallel RGB LCD interface (eLCDIF)
– Support 8/16/24-bit interface
– Support up to WXGA resolution @60fps
– Support Index color with 256 entry x 24-bit color LUT
— Parallel RGB LCD Interface Version 2 (LCDIFv2)
– Enhanced based on LCDIF version
– Support up to 8 layers of alpha blending
— MIPI Display Serial Interface (MIPI DSI)
– PHY integrated
– 2 data lanes interface with up to 1.5 GHz bit rate clock
— Smart LCD Display with 8080 interface through SEMC
• Audio:
— SPDIF input and output
— Four Synchronous Audio Interface (SAI) modules supporting I2S, AC97, TDM, and
codec/DSP interfaces
— Medium Quality Sound (MQS) interface via GPIO pads
— PDM microphone interface with 4 pairs of inputs
— Asynchronous Sample Rate Converter (ASRC)
• Graphics engine:
— Generic 2D (PXP)
– BitBlit
– Flexible image composition options—alpha, chroma key
– Porter-duff blending
– Image rotation (90, 180, 270)
– Image resize
– Color space conversion
– Multiple pixel format support (RGB, YUV444, YUV422, YUV420, YUV400)
– Standard 2D-DMA operation
— Vector Graphics Processing
– Real-time hardware curve tessellation of lines, quadratic, and cubic Bezier curves
– 16x Line Anti-aliasing
– OpenVG 1.1 support
– Vector Drawing
• Camera Interface:
— Parallel Camera Sensor Interface (CSI)
– Support 24-bit, 16-bit, and 8-bit input
– Barcode binarization and histogram statistics
— MIPI Camera Serial Interface (MIPI CSI)
– PHY integrated
– 2 data lanes interface with up to 1.5 GHz bit rate clock
• Connectivity:
— Two USB 2.0 OTG controllers with integrated PHY interfaces
— Two Ultra Secure Digital Host Controller (uSDHC) interfaces
– eMMC 5.0 compliance with HS400 support up to 400 MB/sec
– SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100 MB/sec
– Support for SDXC (extended capacity)
— One 10M/100M Ethernet controller with support for IEEE1588
— One Gigabit Ethernet controller with support for AVB
— Twelve universal asynchronous receiver/transmitter (UARTs) modules
— Six I2C modules
— Six SPI modules
— Three FlexCAN (with Flexible Data-rate supported) modules
— Two EMV SIM modules
• Analog:
— Two Analog-Digital-Converters (ADC), which supports both differential and single-end inputs
— One Digital-Analog-Converter (DAC)
— Four Analog Comparators (ACMP)
• GPIO and Pin Multiplexing:
— General-purpose input/output (GPIO) modules with interrupt capability
— Input/output multiplexing controller (IOMUXC) to provide centralized pad control
— Two FlexIO modules
— 8 x 8 keypad
The i.MX RT1160 processors integrate advanced power management unit and controllers:
• Full PMIC integration, including on-chip DCDC and LDOs
• Temperature sensor with programmable trim points
• Hardware power management controller (GPC)
The i.MX RT1160 processors support the following system debug:
• Arm CoreSight debug and trace architecture
• Trace Port Interface Unit (TPIU) to support off-chip real-time trace
• Cross Triggering Interface (CTI)
• Support for 5-pin (JTAG) and SWD debug interfaces
Security functions are enabled and accelerated by the following hardware:
• High Assurance Boot (HAB)
• Cryptographic Acceleration and Assurance (CAAM) module:
— Public Key Cryptography Engine (PKHA)
— Symmetric Engines
— Cryptographic Hash Engine
— Random Number Generation (RNG4)
— Four Job Rings for use by processors
— Secure Hardware-Only Cryptographic Key Management
— Encrypted Boot
— Revision control check based on fuse values
— DEK includes IV
— Side channel attack countermeasures
— 64 KB secure RAM
• Inline Encryption Engine (IEE):
— External memory encryption/decryption
— I/O direct encrypted storage and retrieval (Stream Support)
— FlexSPI decryption only
• On-the-Fly AES Decryption (OTFAD):
— AES-128 Counter Mode On-the-Fly Decryption
— Hardware support for unwrapping “key blobs”
— Functionally acts as a slave sub-module to the FlexSPI
• Secure Non-Volatile Storage (SNVS):
— Secure real-time clock (SRTC)
— Zero Master Key (ZMK)
• Secure always-on RAM (4 KB)
• Secure key management and protection
— Physical Unclonable Function (PUF)
— UnDocumented Function (UDF)
— Built-in Manufacturing Protection Hardware
• Secure and trusted access control