Features
• 1:9 LVCMOS Output Fanout Buffer from DC to
160 MHz
• Low Additive Phase Jitter of 60 fsRMS
• 8 mA Output Drive Strength
• Low Power Consumption for Portable
Applications
• Low Input-Output Delay
• Output-Output Skew <250 ps
• 2.5V to 3.3V, ±10% Operation
• 1.8V +10%/–5% Operation up to 67 MHz
• Operating Temperature Range: 0°C to +70°C,
–40°C to +85°C, or –40°C to +105°C
• Available in 16-Lead WQFN Package

Applications
• Low Power Applications
• ePPS

General Description
The PL133-97 is an advanced fanout buffer designed
for high performance, low-power, small form factor
applications. The PL133-97 accepts a reference clock
input from DC to 160 MHz and provides nine outputs of
the same frequency with ultra-low additive jitter.
The PL133-97 is offered in a small 3 mm x 3 mm
WQFN-16L package.
The PL133-97 outputs can be disabled to a high
impedance (tri-state) by pulling low the OE pin. When
the OE pin is high, the outputs are enabled and follow
the REF input signal. When the OE pin is left open, a
pull-up resistor on the chip will default the OE pin to
logic 1 so the outputs are enabled.
CLK8 is a free running output that remains enabled
when the OE pin is pulled low.