• Eight low skew, low additive jitter LVPECL output pairs
• Two selectable, differential clock input pairs
• Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz
• LVCMOS interface levels for the control input (input select)
• Output skew: 28ps (typical)
• Propagation delay: 410ps (maximum)
• Low additive phase jitter, RMS: 54.1fs (maximum)
(fREF = 156.25MHz, VPP = 1V, 12kHz–20MHz)
• Full 3.3V and 2.5V supply voltage
• Maximum device current consumption (IEE): 141mA
• Available in lead-free (RoHS 6), 28-Lead VFQFPN package
• -40°C to 85°C ambient operating temperature
• Supports case temperature ≤ 105°C operations
• Differential PCLK0, nPCLK0 and PCLK1, nPCLK1 pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input to Accept Single-Ended Levels
(Figure 1A and Figure 1B)
• Supports PCI Express Gen1–5