Ultra-low power consumption technology
● VDD = single power supply voltage of 1.6 to 5.5 V
● HALT mode
● STOP mode
● SNOOZE mode
RL78 CPU core
● CISC architecture with 3-stage pipeline
● Minimum instruction execution time: Can be
changed from high speed (0.03125 μs: @ 32 MHz
operation with high-speed on-chip oscillator) to
ultra-low speed (30.5 μs: @ 32.768 kHz operation with subsystem clock)
● Address space: 1 MB
● General-purpose registers: (8-bit register × 8) × 4 banks
● On-chip RAM: 24 or 32 KB
Code flash memory
● Code flash memory: 384 or 512 KB
● Block size: 1 KB
● Prohibition of block erase and rewriting (security function)
● On-chip debug function
● Self-programming (with boot swap function/flash shield window function)