300 MHz/450 MHz/600 MHz, MCU with Arm® Cortex®-R4 and -M3*1, on-chip FPU, 498/747/996
DMIPS, up to 1 Mbyte of on-chip extended SRAM, Ethernet MAC, EtherCAT*1, USB 2.0 high-speed,
CAN, various communications interfaces such as an SPI multi-I/O bus controller, ΔΣ interface, safety
functions, encoder interfaces*1, and security functions*1

■ On-chip 32-bit Arm Cortex-R4 processor
 High-speed realtime control with maximum operating frequency of
300/450/600 MHz
Capable of 498/747/996 DMIPS (in operation at 300/450/600
MHz)
 On-chip 32-bit Arm Cortex-R4 (revision r1p4)
 Tightly coupled memory (TCM) with ECC: 512 Kbytes/32 Kbytes
 Instruction cache/data cache with ECC: 8 Kbytes per cache
 High-speed interrupt
 The FPU supports addition, subtraction, multiplication, division,
multiply-and-accumulate, and square-root operations at singleprecision
and double-precision.
 Harvard architecture with 8-stage pipeline
 Supports the memory protection unit (MPU)
 Arm CoreSight architecture, includes support for debugging
through JTAG and SWD interfaces
■ On-chip 32-bit Arm Cortex-M3 processor
(in products incorporating an R-IN engine)
 150-MHz operating frequency
 On-chip 32-bit Arm Cortex-M3 (revision r2p1)
 RISC Harvard architecture with 3-stage pipeline
 Supports the memory protection unit (MPU)