• Two 1:8, low skew, low additive jitter LVPECL fanout buffers
• Two differential clock inputs
• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
accept the following differential input levels: LVDS, LVPECL,
CML
• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
also accept single-ended LVCMOS levels. See Applications
section Wiring the Differential Input Levels to Accept
Single-ended Levels (Figure 1A and Figure 1B).
• Maximum input clock frequency: 2GHz
• Output bank skew: 15ps (typical)
• Propagation delay: 390ps (maximum)
• Low additive phase jitter, RMS: 54fs (maximum)
(fREF = 156.25MHz, VPP = 1V, 12kHz – 20MHz, VCC = 3.3V)
• Full 3.3V and 2.5V supply voltage
• Maximum device current consumption (IEE): 143mA
• Available in Lead-free (RoHS 6), 48-Lead VFQFN package
• Supports case temperature 105°C operations
• -40°C to 85°C ambient operating temperature