▪ 1:18, low skew, low additive jitter LVPECL/LVDS fanout buffer
▪ Low power consumption
▪ Differential PCLK, nPCLK clock pair accepts the following
differential/single-ended input levels: LVDS, LVPECL, and
LVCMOS
▪ Maximum input clock frequency: 2GHz
▪ Propagation delay: 290ps (typical)
▪ Output skew: 40ps (typical)
▪ Low additive phase jitter, RMS: 39fs (typical),
Integration Range: 12kHz – 20MHz,
(fREF  156.25MHz, VPP  1V, VDD  3.3V)
▪ Full 2.5V and 3.3V supply voltage modes
▪ Device current consumption: 180mA (typical) IEE for LVPECL
output mode, 400mA (typical) IDD for LVDS output mode
▪ 48-VFQFPN, lead-free (RoHS 6) packaging
▪ Transistor count: 1762
▪ -40°C to +85°C ambient operating temperature
▪ Supports case temperature up to 105°C