DESCRIPTION
The STLVD210 is a low skew programmable 1-to-5 dual differential LVDS driver, designed with clock distribution in mind. The LVDS input signals can be either differential or single-ended if the VBB output is used.
The STLVD210 is provided with a 11 bit shift register with a serial in and a Control Register. The purpose is to enable or power off each output clock channel and to select the clock input. The STLVD210 is specifically designed, modelled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device. The net result is a dependable guaranteed low skew device.
The STLVD210 can be used for high performance clock distribution in 2.5V systems with LVDS levels. Designers can be take advantage of the device’s performance to distribute low skew clocks across the backplane or the board.

■ 100ps PART-TO-PART SKEW
■ 50ps BANK SKEW
■ DIFFERENTIAL DESIGN
■ MEETS LVDS SPEC. FOR DRIVER OUTPUTS AND RECEIVER INPUTS
■ REFERENCE VOLTAGE AVAILABLE OUTPUT VBB
■ LOW VOLTAGE VCC RANGE OF 2.375V TO 2.625V
■ HIGH SIGNALLING RATE CAPABILITY (EXCEEDS 700MHz)
■ SUPPORT OPEN, SHORT, AND TERMINATED INPUT FAIL-SAFE (LOW OUTPUT STATE)
■ PROGRAMMABLE DRIVERS POWER OFF CONTROL