GENERAL DESCRIPTION
The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

FEATURES
    Fully integrated dual VCO/PLL cores
        0.22 ps rms jitter from 0.637 MHz to 10 MHz at 106.25 MHz
        0.19 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
        0.42 ps rms jitter from 12 kHz to 20 MHz at 125 MHz
        Input crystal or clock frequency of 25 MHz
    Preset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz, 100 MHz, and 125 MHz
    Choice of LVPECL or LVDS output format
    Integrated loop filters
    Copy of reference clock output
    Rates configured via strapping pins
    0.71 W power dissipation (LVDS operation)
    1.07 W power dissipation (LVPECL operation)
    3.3 V operation
    Space saving, 6 mm × 6 mm, 40-lead LFCSP

APPLICATIONS
    Fiber channel line cards, switches, and routers
    Gigabit Ethernet/PCIe support included
    Low jitter, low phase noise clock generation