DESCRIPTION
The Aeroflex ACT5261 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative TLB, a 32 KByte 2-way set associative instruction cache, a 32 KByte 2-way set associative data cache, and a high-performance 64-bit system interface. The ACT5261 can issue both an integer and a floating point instruction in the same cycle.

Features
■ Full militarized QED RM5261 microprocessor
■ Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle
    ● 133, 150, 200, 250 MHz operating frequencies – Consult Factory for latest speeds
    ● 345 Dhrystone 2.1 MIPS
    ● SPECInt95 7.3, SPECfp95 8.3
■ Pinout compatible with popular RM5260
■ High performance system interface compatible with RM5260, RM 5270, RM5271, RM7000, R4600, R4700 and R5000
    ● 64-bit multiplexed system address/data bus for optimum price/performance
    ● High performance write protocols maximize uncached write bandwidth
    ● Supports 1/2 clock divisors (2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9)
    ● IEEE 1149.1 JTAG boundary scan
■ • Integrated on-chip caches
    ● 32KB instruction - 2 way set associative
    ● 32KB data - 2 way set associative
    ● Virtually indexed, physically tagged
    ● Write-back and write-through on per page basis
    ● Pipeline restart on first double for data cache misses
■ • Integrated memory management unit
    ● Fully associative joint TLB (shared by I and D translations)
    ● 48 dual entries map 96 pages
    ● Variable page size (4KB to 16MB in 4x increments)
■ High-performance floating point unit: up to 500 MFLOPS
    ● Single cycle repeat rate for common single precision operations and some double precision operations
    ● Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations
    ● Single cycle repeat rate for single precision combined multiplyadd operation
■ • MIPS IV instruction set
    ● Floating point multiply-add instruction increases performance in signal processing and graphics applications
    ● Conditional moves to reduce branch frequency
    ● Index address modes (register + register)
■ Embedded application enhancements
    ● Specialized DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction
    ● I and D cache locking by set
    ● Optional dedicated exception vector for interrupts
■ Fully static CMOS design with power down logic
    ● Standby reduced power mode with WAIT instruction
    ● 3.6 Watts typical power @ 200MHz
    ● 2.5V core with 3.3V IO’s
■ 208-lead CQFP, cavity-up package (F17)
■ 208-lead CQFP, inverted footprint (F24), Intended to duplicate the commercial QED footprint
■ 179-pin PGA package (Future Product) (P10)