GENERAL DESCRIPTION
The MT28F321P20 and MT28F321P18 are high-performance, high-density, nonvolatile memory solutions that can significantly improve system performance. This new architecture features a two-memory-bank configuration that supports background operation with no latency.
A high-performance bus interface allows a fast page mode, data transfer; a conventional asynchronous bus interface is provided as well.
The devices allow soft protection for blocks, as read only, by configuring soft protection registers with dedicated command sequences. For security purposes, two 64-bit chip protection registers are provided.

FEATURES
• Flexible dual-bank architecture
   Support for true concurrent operation with zero
      latency
   Read bank a during program bank b and vice
      versa
   Read bank a during erase bank b and vice versa
• Basic configuration:
   Seventy-one erasable blocks
   Bank a (4Mb for data storage)
   Bank b (28Mb for program storage)
• VCC, VCCQ, VPP voltages*
   1.70V (MIN), 1.90V (MAX) VCC, VCCQ
      (MT28F321P18)
   1.80V (MIN), 2.20V (MAX) VCC, VCCQ
      (MT28F321P20)
   0.9V (MIN) VPP (in-system PROGRAM/ERASE)
   12V ±5% (HV) VPP tolerant (factory
      programming compatibility)
• Random access time: 70ns and 80ns @ 1.80V VCC*
• Page Mode read access*
   Eight-word page
   Interpage read access: 70ns/80ns @ 1.80V
   Intrapage read access: 30ns @ 1.80V
• Low power consumption (VCC = 2.20V)
   Asynchronous READ < 15mA
   Standby < 50µA
      Automatic power save (APS) feature
• Enhanced write and erase suspend options
   ERASE-SUSPEND-to-READ within same bank
   PROGRAM-SUSPEND-to-READ within same bank
   ERASE-SUSPEND-to-PROGRAM within same bank
• Dual 64-bit chip protection registers for security
   purposes
• Cross-compatible command support
   Extended command set
   Common flash interface
• PROGRAM/ERASE cycle
   100,000 WRITE/ERASE cycles per block