The DSP56156 is a general-purpose MPU-style Digital Signal Processor (DSP). On a single semiconductor chip, the DSP56156 comprises a very efficient 16-bit digital signal processing core, program and data memories, a number of peripherals, and system support circuitry. Unique features of the DSP56156 include a built-in sigma-delta (²ý) codec and phase-locked loop (PLL). This combination of features makes the DSP56156 a cost-effective, high-performance solution for many DSP applications, especially speech coding, digital communications, and cellular base stations.

DSP56156 Features
Digital Signal Processing Core
• Efficient, object code compatible, 16-bit 56100-Family DSP engine
    — Up to 30 Million Instructions Per Second (MIPS) – 33 ns instruction cycle at 60 MHz
    — Up to 180 Million Operations Per Second (MOPS) at 60 MHz
    — Highly parallel instruction set with unique DSP addressing modes
    — Two 40-bit accumulators including extension byte
    — Parallel 16 × 16-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
    — Double precision 32 × 32-bit multiply with 72-bit result in 6 instruction cycles
    — Least Mean Square (LMS) adaptive loop filter in 2 instructions
    — 40-bit Addition/Subtraction in 1 instruction cycle
    — Fractional and integer arithmetic with support for multiprecision arithmetic
    — Hardware support for block-floating point FFT
    — Hardware-nested DO loops including infinite loops
    — Zero-overhead fast interrupts (2 instruction cycles)
    — Three 16-bit internal data buses and three 16-bit internal address buses for maximum information transfer on-chip

Memory
• On-chip Harvard architecture permitting simultaneous accesses to program and memories
• 2048 × 16-bit on-chip program RAM and 64 × 16-bit bootstrap ROM (or 12 k × 16-bit on-chip program ROM on the DSP56156ROM)
• 2048 × 16-bit on-chip data RAM
• External memory expansion with 16-bit address and data buses
• Bootstrap loading from external data bus, Host Interface, or Synchronous Serial Interface

Peripheral and Support Circuits
• Byte-wide Host Interface (HI) with Direct Memory Access support
• Two Synchronous Serial Interfaces (SSI) to communicate with codecs and synchronous serial devices
    — Built in µ-law and A-law compression/expansion
    — Up to 32 software-selectable time slots in network mode
• 16-bit Timer/Event Counter also generates and measures digital waveforms
• On-chip sigma-delta voice band Codec:
    — Sampling clock rates between 100 kHz and 3 MHz
    — Four software-programmable decimation/interpolation ratios
    — Internal voltage reference ( 2/5 of positive power supply)
    — No external components required

• On-chip peripheral registers memory mapped in data memory space
• Double buffered peripherals
• Up to 27 general purpose I/O pins
• Two external interrupt request pins
• On-Chip Emulation (OnCE™) port for unobtrusive, processor speed-independent debugging
• Software-programmable, Phase-Locked Loop-based (PLL) frequency synthesizer for the core clock

Miscellaneous Features
• Power-saving Wait and Stop modes
• Fully static, HCMOS design for operating frequencies from 40 or 60 MHz down to DC
• 112-pin Ceramic Quad Flat Pack (CQFP) surface-mount package; 20 × 20 × 3 mm
• 112-pin Plastic Thin Quad Flat Pack (TQFP) surface-mount package; 20 × 20 × 1.5 mm
• 5 V power supply