TS68040MFDSLASHT33A datasheet(21/49 Pages) ATMEL

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TS68040

2116A–HIREL–09/02

Notes:

1. Output timing is specified for a valid signal measured at the pin. Large buffer timing is specified driving a 50

Ω transmission

line with a length characterized by a 2.5 ns one-way propagation delay, terminated through 50

Ω to 2.5V. Large buffer output

impedance is typically 3

Ω, resulting in incident wave switching for this environment. Small buffer timing is specified driving

an unterminated 30

Ω transmission line with a length characterized by a 2.5 ns one-way propagation delay. Small buffer out-

put impedance is typically 30

Ω; the small buffer specifications include approximately 5 ns for the signal to propagate the

length of the transmission line and back.

2. All testing to be performed using worst-case test conditions unless otherwise specified.

3. The following pins are active low: AVEC, BG, BS, BR, CDIS, CIOUT, IPEND, IPLO, IPL1, IPL2, LOCK, LOCKE, MDIS, MI,

RST0, RSTI, TA, TBI, TCI, TEA, TIP, TRST, TS and W of R/W.

4. Maximum operating junction temperature (T

J) = +125°. Minimum case operating temperature (TC) = -55°. This device is not

tested at T

C = +125°. Testing is performed by setting the junction temperature TJ = +125°and allowing the case and ambient

temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature.

5. Timing specifications 11, 20 and 38 for address bus output timing apply when normal bus operation is selected. Specifica-

tions 26, 27 and 28 should be used when the multiplexed bus mode of operation is enabled.

6. Timing specifications 18 and 19 for data bus output timing apply when normal bus operation is selected. Specifications 28

and 29 should be used when the multiplexed bus mode of operation is enabled.

Table 15. Input AC Timing Specifications (Figure 9 to Figure 15)

-55°C

≤T

C ≤TJmax; 4.75V ≤VCC ≤5.25V unless otherwise specified

(1)(2)(3)(4)

Num

Characteristic

25 MHz

33 MHz

Unit

Min.

Max.

Min.

Max.

Data-in Valid to BCLK (Setup)

BCLK to Data-in Invalid (Hold)

BCLK to Data-in High Impedance (Read Followed By Write)

36.5

22a

TA Valid to BCLK (Setup)

22b

TEA Valid to BCLK (Setup)

22c

TCI Valid to BCLK (Setup)

22d

TBI Valid to BCLK (Setup)

BCLK to TA, TEA, TCI, TBI Invalid (Hold)

AVEC Valid to BCLK (Setup)

BCLK to AVEC Invalid (Hold)

DLE Width High

Data-in Valid to DLE (Setup)

DLE to Data-in Invalid (Hold)

BCLK to DLE Hold

DLE High to BCLK

Data-in Valid to BCLK (DLE Mode Setup)

BCLK Data-in Invalid (DLE Mode Hold)

41a

BB Valid to BCLK (Setup)

41b

BG Valid to BCLK (Setup)

41c

CDIS, MDIS Valid to BCLK (Setup)

41d

IPLn Valid to BCLK (Setup)

BCLK to BB, BG, CDIS, IPLn, MDIS Invalid (Hold)

44a

Address Valid to BCLK (Setup)

44b

SIZn Valid BCLK (Setup)

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