MSP432P411VIPZR datasheet(64/212 Pages) TI1

64 / 212 page

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Specifications

Table 5-24 lists the characteristics of the normal-drive digital outputs. See Figure 5-19, Figure 5-20,

Figure 5-21, and Figure 5-22 for the typical characteristics graphs.

(1)

The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

specified.

(2)

The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage

drop specified.

(3)

The port can output frequencies at least up to the specified limit - it might support higher frequencies.

(4)

A resistive divider with 2 × R1 and R1 = 3.2 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the

divider. CL = 20 pF is connected to the output to VSS.

(5)

The output voltage reaches at least 20% and 80% VCC at the specified toggle frequency.

(6)

Measured from 20% of VCC to 80% of VCC.

(7)

Measured from 80% of VCC to 20% of VCC.

Table 5-24. Digital Outputs, Normal I/Os

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

UNIT

VOH

High-level output voltage

I(OHmax) = –1 mA

(1)

2.2 V

VCC – 0.25

VCC

I(OHmax) = –3 mA

(2)

VCC – 0.60

VCC

I(OHmax) = –2 mA

(1)

3.0 V

VCC – 0.25

VCC

I(OHmax) = –6 mA

(2)

VCC – 0.60

VCC

VOL

Low-level output voltage

I(OLmax) = 1 mA

(1)

2.2 V

VSS

VSS + 0.25

I(OLmax) = 3 mA

(2)

VSS

VSS + 0.60

I(OLmax) = 2 mA

(1)

3.0 V

VSS

VSS + 0.25

I(OLmax) = 6 mA

(2)

VSS

VSS + 0.60

fPx.y

Port output frequency (with RC

load)(3)

VCORE = 1.4 V, CL = 20 pF, RL

(4) (5)

1.62 V

MHz

2.2 V

3.0 V

dPx.y

Port output duty cycle (with RC

Load)

VCORE = 1.4 V, CL = 20 pF, RL

(4) (5)

1.62 V

40%

60%

2.2 V

40%

60%

3.0 V

45%

55%

fPort_CLK

Clock output frequency(3)

VCORE = 1.4 V, CL = 20 pF

(5)

1.62 V

MHz

2.2 V

3.0 V

dPort_CLK

Clock output duty cycle

VCORE = 1.4 V, CL = 20 pF

(5)

1.62 V

40%

60%

2.2 V

40%

60%

3.0 V

45%

55%

trise,dig

Port output rise time, digital only

port pins

CL = 20 pF

(6)

1.62 V

2.2 V

3.0 V

tfall,dig

Port output fall time, digital only

port pins

CL = 20 pF

(7)

1.62 V

2.2 V

3.0 V

trise,ana

Port output rise time, port pins

with shared analog functions

CL = 20 pF

(6)

1.62 V

2.2 V

3.0 V

tfall,ana

Port output fall time, port pins

with shared analog functions

CL = 20 pF

(7)

1.62 V

2.2 V

3.0 V

MSP432P411VIPZR Datenblatt(PDF) 64 Page - Texas Instruments

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