RAMK027 S

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Vishay MCB

Revision: 29-Aug-17

4

Document Number: 32549

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ELECTRICAL INTERFACE DESCRIPTION - SSI INTERFACE

Timing Diagram

OPTIONS

• Other design on request (mechanical interfaces, electrical interfaces, ...)

6 WIRES CONNECTIONS

NAME

WIRE COLOR

GND

Black

+5 V

Red

CLK+

White

CLK-

Clear

DATA+

Yellow

DATA-

Green

SSI PARAMETERS

Output code

Binary

Data differential interface

RS422 according to EIA-RS422

CLK differential interface

RS422 according to EIA-RS422

Minimum clock frequency

300 kHz

Maximum clock frequency

4 MHz

Data bit (n)

17 bits

Master system

Sensor

+5 V

+5 V

+5 V

+5 V

100

Ω

+5 V

+5 V

GND

+5 V

DATA+

DATA-

CLK-

CLK+

t

1

F

clock

t

≥ 500 ns

t

≤ 200 ns

Start of cycle

End of cycle

CLK+

CLK-

DATA+

0

1

2

14

15

16

DATA-

MSB

LSB