PC755CVGU366LE datasheet(12/50 Pages) ATMEL

12 / 50 page

PC755/745

2138D–HIREL–06/03

Notes:

1. OVDD supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and

L2ZZ); L2OV

DD supplies power to the L2 cache interface (L2ADDR[0-16], L2DATA[0-63], L2DP[0-7] and L2SYNC-OUT)

and the L2 control signals; and VDD supplies power to the processor core and the PLL and DLL (after filtering to become

AVDD and L2AVDD respectively). These columns serve as a reference for the nominal voltage supported on a given signal as

selected by the BVSEL/L2VSEL pin configurations of Table 4 and the voltage supplied. For actual recommended value of

VIN or supply voltages see Table 5.

2. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.

3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OV

(selects 3.3V) or to OGND (selects 1.8V/2.0V).

4. These pins are reserved for potential future use as additional L2 address pins.

5. Uses one of 9 existing no

-connects in PC750’s 360-BGA package.

6. Internal pull up on die.

7. Internally tied to L2OV

DD in the PC755 360-BGA package to indicate the power present at the L2 cache interface. This sig-

nal is not a power supply input.

8. This is different from the PC745 255-BGA package.

TEA

Low

Input

–

TLBISYNC

Low

Input

–

TMS(6)

High

Input

–

TRST(6)

A10

Low

Input

–

Low

I/O

–

TSIZ[0

-2]

A9, B9, C9

High

Output

–

TT[0

-4]

C10, D11, B12, C12, F11

High

I/O

–

Low

Output

–

VDD

G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12

–

VOLTDET(7)

K13

High

Output

–

Table 2. Pinout Listing for the PC755, 360 PBGA, CBGA and CI-CGA Packages + HiTCE

(8) (Continued)

Signal Name

Pin Number

Active

I/O

I/F Voltages

Supported(1)

1.8V/2.0V

3.3V

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