PSD813F2 datasheet(88/110 Pages) STMICROELECTRONICS

88 / 110 page

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

88/110

Table 55. READ Timing (5V devices)

Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.

2. RD and PSEN have the same timing.

3. Any input used to select an internal PSD function.

4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.

5. RD timing has the same timing as DS, LDS, and UDS signals.

Symbol

Parameter

Conditions

-70

-90

-15

Turbo

Off

Unit

MinMax

tLVLX

ALE or AS Pulse Width

tAVLX

Address Setup Time

(Note 3)

tLXAX

Address Hold Time

(Note 3)

tAVQV

Address Valid to Data Valid

(Note 3)

150

+ 10

tSLQV

CS Valid to Data Valid

100

150

tRLQV

RD to Data Valid 8-Bit Bus

(Note 5)

RD or PSEN to Data Valid

8-Bit Bus, 8031, 80251

(Note 2)

tRHQX

RD Data Hold Time

(Note 1)

tRLRH

RD Pulse Width

(Note 1)

tRHQZ

RD to Data High-Z

(Note 1)

tEHEL

E Pulse Width

tTHEH

R/W Setup Time to Enable

tELTL

R/W Hold Time After Enable

tAVPV

Address Input Valid to

Address Output Delay

(Note 4)

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