P8XC557E8 datasheet(8/84 Pages) PHILIPS

8 / 84 page

1999 Mar 12

Philips Semiconductors

Product speciﬁcation

8-bit microcontroller

P8xC557E8

6.2

Pin description

Table 1

Pin description for QFP80 (SOT318-2)

To avoid a ‘latch-up’ effect at power-on: VSS − 0.5 V < ‘voltage at any pin at any time’ < VDD + 0.5 V.

SYMBOL

DESCRIPTION

Vref(n)(A)

Low-end of ADC reference resistor.

Vref(p)(A)

High-end of ADC reference resistor.

VSSA1

Ground, analog part. For ADC receiver and reference voltage.

VDDA1

Power supply, analog part (+5 V). For ADC receiver and reference voltage.

P5.7/ADC7 to

P5.0/ADC0

5to12

Port 5 (P5.7 to P5.0): 8-bit input port lines;

ADC7 to ADC0: 8 input channels to the ADC.

VSS1 to VSS4

13, 29,

54, 67

Ground; digital part; circuit ground potential. VSS1, VSS2, VSS4 must be connected,

VSS3 is internally connected to digital ground, but should be connected externally.

VDD1 to VDD4

14, 28,

53, 66

Power supply, digital part (+5 V). Power supply pins during normal operation and

power reduction modes. All pins must be connected.

ADEXS

Start ADC operation. Input starting ADC, triggered by a programmable edge; ADC

operation can also be started by software. This pin must not ﬂoat.

PWM0

Pulse Width Modulation output 0.

PWM1

Pulse Width Modulation output 1.

Enable Watchdog Timer (WDT): enable for T3 Watchdog Timer and disable

Power-down mode. This pin must not ﬂoat.

P4.0/CMSR0 to

P4.5/CMSR5

19 to 22,

24, 25

Port 4 (P4.0 to P4.7): 8-bit quasi-bidirectional I/O port lines;

CMSR0 to CMSR5: compare and set/reset outputs for Timer T2;

CMT0 to CMT1: compare and toggle outputs for Timer T2.

P4.6/CMT0 to

P4.7/CMT1

26, 27

RSTOUT

Reset output of the P8xC557E8 for resetting peripheral devices during initialization

and Watchdog Timer overﬂow.

RSTIN

Reset input to reset the P8xC557E8.

P1.0/CT0I/INT2 to

P1.3/CT3I/INT5

31 to 34

Port 1 (P1.0 to P1.7): 8-bit quasi-bidirectional I/O port lines;

CT0I to CT3I: Capture timer inputs for Timer T2;

INT2 to INT5: external interrupts 2 to 5;

T2: T2 event input (rising edge triggered);

RT2: T2 timer reset input (rising edge triggered).

P1.4/T2 to

P1.5/RT2

35, 36

P1.6 to P1.7

37 to 38

SCL

I2C-bus serial clock I/O port. If SCL is not used, it must be connected to VSS.

SDA

I2C-bus serial data I/O port. If SDA is not used, it must be connected to VSS.

P3.0/RXD

Port 3 (P3.0 to P3.7): 8-bit quasi-bidirectional I/O port lines;

RXD: Serial input port;

TXD: Serial output port;

INT0: External interrupt input 0;

INT1: External interrupt input 1;

T0: Timer 0 external interrupt input;

T1: Timer 1external interrupt input;

WR: External Data Memory Write strobe;

RD: External Data Memory Read strobe.

P3.1/TXD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

n.c.

49, 50

Not connected pins.

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