AD7783 datasheet(4/12 Pages) AD

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REV. B

–4–

AD7783

Limit at TMIN, TMAX

Parameter

(B Version)

Unit

Conditions/Comments

30.5176

ms typ

Crystal Oscillator Period

tADC

50.54

ms typ

19.79 Hz Update Rate

ns min

CS Falling Edge to DOUT Active

ns max

VDD = 4.75 V to 5.25 V

ns max

VDD = 2.7 V to 3.6 V

¥ tADC

ns typ

Channel Settling Time

ns min

SCLK Active Edge to Data Valid Delay

ns max

VDD = 4.75 V to 5.25 V

ns max

VDD = 2.7 V to 3.6 V

ns min

Bus Relinquish Time after

CS Inactive Edge

ns max

ns min

CS Rising Edge to SCLK Inactive Edge Hold Time

ns min

SCLK Inactive to DOUT High

ns max

Slave Mode Timing

100

ns min

SCLK High Pulse Width

100

ns min

SCLK Low Pulse Width

Master Mode Timing

t1/2

ms typ

SCLK High Pulse Width

t1/2

ms typ

SCLK Low Pulse Width

t10

t1/2

ms min

DOUT Low to First SCLK Active Edge

3t1/2

ms max

NOTES

1Sample tested during initial release to ensure compliance. All input signals are specified with t

R = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2See Figure 2.

3These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V

OL or VOH limits.

4SCLK active edge is falling edge of SCLK.

5These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then

extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means the times quoted in the timing characteristics are the true bus relin-

quish times of the part and as such are independent of external bus loading capacitances.

TIMING CHARACTERISTICS1, 2 (V

DD = 2.7 V to 3.6 V or VDD = 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz;

Input Logic 0 = 0 V, Logic 1 = VDD, unless otherwise noted.)

TO OUTPUT

50pF

ISINK (1.6mA WITH VDD = 5V

100 A WITH VDD = 3V)

1.6V

ISOURCE( 200 A WITH VDD = 5V

100 A WITH VDD = 3V)

Figure 1. Load Circuit for Timing Characterization

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