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MB91F467BA Datenblatt(PDF) 91 Page - Cypress Semiconductor |
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MB91F467BA Datenblatt(HTML) 91 Page - Cypress Semiconductor |
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91 / 127 page ![]() MB91460B Series Document Number: 002-04608 Rev. *A Page 90 of 126 1. The Interrupt Control Registers (ICRs) are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is provided for each interrupt request. 2. The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR) . The TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value (000FFC00H) . The TBR is initialized to this value by a reset. The TBR is set to 000FFC00H after the internal boot ROM is executed. 3. ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0]) 4. Used by REALOS 5. Memory Protection Unit (MPU) support PPG 2 114 72 ICR49 471H 234H 000FFE34H 98 PPG 3 115 73 230H 000FFE30H 99 PPG 4 116 74 ICR50 472H 22CH 000FFE2CH 100 PPG 5 117 75 228H 000FFE28H 101 PPG 6 118 76 ICR51 473H 224H 000FFE24H 102 PPG 7 119 77 220H 000FFE20H 103 PPG 8 120 78 ICR52 474H 21CH 000FFE1CH 104 PPG 9 121 79 218H 000FFE18H 105 PPG 10 122 7A ICR53 475H 214H 000FFE14H 106 PPG 11 123 7B 210H 000FFE10H 107 PPG 12 124 7C ICR54 476H 20CH 000FFE0CH 108 PPG 13 125 7D 208H 000FFE08H 109 PPG 14 126 7E ICR55 477H 204H 000FFE04H 110 PPG 15 127 7F 200H 000FFE00H 111 Up/Down Counter 0 128 80 ICR56 478H 1FCH 000FFDFCH — Up/Down Counter 1 129 81 1F8H 000FFDF8H — Reserved 130 82 ICR57 479H 1F4H 000FFDF4H — Reserved 131 83 1F0H 000FFDF0H — Real Time Clock 132 84 ICR58 47AH 1ECH 000FFDECH — Calibration Unit 133 85 1E8H 000FFDE8H — A/D Converter 0 134 86 ICR59 47BH 1E4H 000FFDE4H 14, 112 System reserved 135 87 1E0H 000FFDE0H — Alarm Comparator 0 136 88 ICR60 47CH 1DCH 000FFDDCH — Reserved 137 89 1D8H 000FFDD8H — Low Voltage Detection 138 8A ICR61 47DH 1D4H 000FFDD4H — Reserved 139 8B 1D0H 000FFDD0H — Time base Overflow 140 8C ICR62 47EH 1CCH 000FFDCCH — PLL Clock Gear 141 8D 1C8H 000FFDC8H — DMA Controller 142 8E ICR63 47FH 1C4H 000FFDC4H — Main/Sub OSC stability wait 143 8F 1C0H 000FFDC0H — Security vector 144 90 — — 1BCH 000FFDBCH — Used by the INT instruction. 145 to 255 91 to FF —— 1B8H to 000H 000FFDB8H to 000FFC00H — Interrupt Interrupt number Interrupt level [1] Interrupt vector [2] DMA Resource number Decimal Hexa- decimal Setting Register Register address Offset Default vector address |
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