5220-DS02-R datasheet(81/90 Pages) BOARDCOM

81 / 90 page

Preliminary Data Sheet

BCM5220

04/20/04

Broa d c om Co rp o r a t i o n

Document

5220-DS04-405-R

Auxiliary Status 4 Register (Shadow Register)

Page 69

RMII transmit timing parameters are described in Table 50 and Figure 16 illustrates the RMII management transmit timing.

Figure 16: RMII Transmit Packet Timing

RMII receive timing parameters are described in Table 51 and Figure 17 illustrates the RMII management receive timing.

Table 50: RMII Transmit Timing

Parameter

Symbol

Min

Typ

Max

Unit

REF_CLK Cycle Time

TXEN, TXER, TXD[1:0] Setup Time to

REF_CLK rising

TXEN_SETUP

TXEN, TXER, TXD[1:0] Hold Time from

REF_CLK rising

TXEN_HOLD

Notes:

1. TXD[1:0] provides valid data for each REF_CLK period while TX_EN is asserted.

2. As the REF_CLK frequency is 10 times the data rate in 10Mbps mode, the value on TXD[1:0] is valid so that TXD[1:0]

can be sampled every 10th cycle, regardless of the starting cycle within the group, and yield the correct frame data.

Table 51: RMII Receive Timing

Parameter

Symbol

Min

Typ

Max

Unit

REF_CLK Cycle Time

RXD[1:0], RXER, CRS_DV Output delay from

REF_CLK Rising

216

Notes:

1. As the REF_CLK frequency is 10 times the data rate in 10-Mbps mode, the value on RXD[1:0] is valid so that RXD[1:0]

can be sampled every 10th cycle, regardless of the starting cycle within the group, and yield the correct frame data.

2. The receiver accounts for differences between the local REF_CLK and the recovered clock through use of sufficient

elasticity buffering.

3. The output delay is with a load of 25 PF, which accommodates a PCB trace length of over 12 inches.

TXD[1]

TXD[0]

TX_EN

REF_CLK

Preamble

Data

SFD

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