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54LS114 Datenblatt(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Teilenummer 54LS114
Bauteilbeschribung  Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
PDF  6 Pages
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Hersteller  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

54LS114 Datenblatt(HTML) 3 Page - National Semiconductor (TI)

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Electrical Characteristics (Continued)
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 1)
IIL
Low Level Input Current
VCC e Max VI e 04V Jn Kn Inputs
b
04
mA
SD1 SD2 Inputs
b
08
mA
CD Input
b
16
mA
CP Input
b
144
mA
IOS
Short Circuit
VCC e Max
b
20
b
100
mA
Output Current
(Note 2)
ICC
Supply Current
VCC e Max VCP e 0V
80
mA
Note 1
All typicals are at VCC e 5V TA e 25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second
Switching Characteristics
VCC ea50V TA ea25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
RL e 2k CL e 15 pF
Units
Min
Max
fmax
Maximum Count Frequency
30
MHz
tPLH
Propagation Delay
16
ns
tPHL
CP toQorQ
24
tPLH
Propagation Delay
16
ns
tPHL
CD or SDntoQorQ
24
Truth Table
Inputs
Output
tn
tna1
JK
Q
LL
Qn
LH
L
HL
H
HH
Qn
Asynchronous Inputs
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD
makes both Q and Q HIGH
H e HIGH Voltage Level
L e LOW Voltage Level
tn e Bit time before clock pulse
tna1 e Bit time after clock pulse
3



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