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LT1952

1952f

BLOCK DIAGRA

TI I G DIAGRA

VREF

>90%

–

SOURCE

2.5mA

2.5V

1.23V

(100 TO 500)kHz

OSC

(TYPICAL 200kHz)

IHYST

11µA SD_VSEC = 1.32V

0µA SD_VSEC > 1.32V

SD_VSEC

ROSC

SYNC

1.32V

1.23V

ADAPTIVE

MAXIMUM

DUTY CYCLE

CLAMP

(LINEAR)

SLOPE COMP

8µA 0% DC

35µA 80% DC

RAMP

BLANK

COMP

GND

BLANK

DELAY

VREF

VIN

SS_MAXDC

SOFT-START CONTROL

OVER

CURRENT

SENSE

CURRENT

OUT

16 SOUT

PGND

ISENSE

11 OC

DRIVER

±1A

±50mA

12V

13V

0.45V

1952 BD

–

(VOLTAGE)

ERROR AMPLIFIER

100mV

0mV TO 220mV

DELAY

14.25V ON

8.75V OFF

460µA START-UP

INPUT CURRENT

–

Figure 2. Block Diagram

1952 F01

tDELAY: PROGRAMMABLE SYNCHRONOUS DELAY

FAULTS TRIGGERING SOFT-START

VIN < 8.75V

SD_VSEC < 1.32V (UVLO)

OC > 100mV (OVER-CURRENT)

SOFT-START LATCH RESET:

VIN > 14.25V (> 8.75V IF LATCH SET BY OC)

AND

SD_VSEC > 1.32V

AND

OC < 100mV

AND

SS_MAXDC < 0.45V

SOFT-START

LATCH SET

SOUT

OUT

SS_MAXDC

0.8V (ACTIVE THRESHOLD)

0.45V (RESET THRESHOLD)

0.2V

Figure 1. Timing Diagram

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