SI9241 datasheet(3/7 Pages) VISHAY

3 / 7 page

Document Number: 70787

S11-0975-Rev. F, 16-May-11

www.vishay.com

Vishay Siliconix

Si9241A

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

End of Life. Last Available Purchase Date is 31-Dec-2014

Notes:

a. Room = 25 °C, Cold and Hot = as determined by the operating temperature suffix.

b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

d. Guaranteed by design, not subject to production test.

e. Minimum pulse width to reset a fault condition.

f. High referes to Logic High and Low refers to Logic Low.

SPECIFICATIONS

Parameter

Symbol

Test Conditions Unless Specified

VDD = 4.5 V to 5.5 V

VBAT = 6 V to 36 V

Limits

- 40 to 125 °C

Unit

Temp.a

Min.b

Typ.c

Max.b

Transmitter and Logic Levels

CS, TX Input Low Voltage

VILT

Full

1.5

CS, TX Input High Voltage

VIHT

Full

3.5

TX Input Capacitanced

CINT

Full

CS, TX Input Pull-up Resistance

RTX,

VDD = 5.5 V, TX or CS = 1.5 V, 3.5 V

Full



K Transmit

K Output Low Voltage

VOLK

RL = 510  ± 5 %, VBAT = 6 to 18

Full

0.2 VBAT

RL = 1 k ± 5 %, VBAT = 16 to 36

Full

0.2 VBAT

RL = 510  ± 5 %, VBAT = 4.5

Full

1.2

K Output High Voltage

VOHK

RL = 510  ± 5 %, VBAT = 4.5 to 18

Full

0.95 VBAT

RL = 1 k ± 5 %, VBAT = 16 to 36

Full

0.95 VBAT

K Rise, Fall Times

tr, tf

See Test Circuit

Full

9.6

µs

K Output Sink Resistance

Rsi

CS = 0 V, TX = 0 V

Full

110



K Output Capacitanced

Full

Receiver

K Input Low Voltage

VILK

Full

0.35 VBAT

K Input High Voltage

VIHK

Full

0.65 VBAT

K Input Hysteresisc, d

VHYS

Full

0.05 VBAT

K Input Currents

IIHK

CS = 4

VIHK = VBAT

Full

µA

RX Output Low Voltage

VOLR

VILK = 0.35 VBAT

IOLR = 1 mA

Full

0.4

RX Pull-up Resistance

RRX

Full



RX Turn On Delay

td(on)

RL = 510  ± 5 %, VBAT = 6 V to 18 V

CL = 10 nF, See Test Circuit

Full

µs

RL = 1 k ± 5 %, VBAT = 16 V to 36 V

CL = 4.7 nF, See Test Circuit

Full

RX Turn Off Delay

td(off)

RL = 510  ± 5 %, VBAT = 6 V to 18 V

CL = 10 nF, See Test Circuit

Full

RL = 1 k ± 5 %, VBAT = 16 V to 36 V

CL = 4.7 nF, See Test Circuit

Full

Supplies

Bat Supply Current On

IBAT(on)

CS = TX = 0 V, VBAT  16 V

Full

1.2

Bat Supply Current Off

IBAT(off)

CS = High, VBAT  12 V, TX = High

Full

120

220

µA

Bat Supply Current Standby

IBAT(SB)

VDD  0.5 V, VBAT  12 V

Full

< 1

Logic Supply Current On

IDD(on)

VDD  5.5 V, TX = 0 V

Full

1.4

2.3

Logic Supply Current Off

IDD(off)

CS = High, VBAT  12 V, TX = High

Full

µA

Miscellaneous

TX Transmit Baud Rate

BRT

RL = 510 , CL = 10 nF

Full

10.4

kBaud

RX Receive Baud Ratec

BRR

6 V < VBAT < 16 V, CRX = 20 pF

Full

200

Transmission Frequency

fK-RXK

6 V < VBAT < 16 V, RK = 510 , CK  1.3 nF

Full

200

kHz

Fault Output Low Voltage

VOLF

CS = TX = 0, K = VBAT, IOLF = 1 mA

Full

0.4

CS Minimum Pulse Widthd, e

tcs

Full

µs

Over Temperature Shutdownd

TSHUT

Temperature Rising

160

180

°C

Temperature Shutdown Hysteresisc

THYST

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