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IC62C1024 Datenblatt(PDF) 6 Page - Integrated Circuit Solution Inc

Teilenummer IC62C1024
Bauteilbeschribung  128K X 8 HIGH SPEED CMOS STATIC RAM
PDF  8 Pages
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Hersteller  ICSI [Integrated Circuit Solution Inc]
Direct Link  http://www.icsi.com.tw
Logo ICSI - Integrated Circuit Solution Inc

IC62C1024 Datenblatt(HTML) 6 Page - Integrated Circuit Solution Inc

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Integrated Circuit Solution Inc.
ALSR005-0A
1+$ + "
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low
Power)
-35
-45
-55
-70
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
tWC
Write Cycle Time
35
—
45
—
55
—
70
—
ns
tSCE
CE1 to Write End
25
—
35
—
50
—
60
—
ns
tSCE
CE2 to Write End
25
—
35
—
50
—
60
—
ns
tAW
Address Setup Time to Write End
25
—
35
—
45
—
60
—
ns
tHA
Address Hold from Write End
0
—
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
0
—
0
—
ns
tPWE" WE Pulse Width
25
—
35
—
40
—
50
—
ns
tSD
Data Setup to Write End
20
—
25
—
25
—
30
—
ns
tHD
Data Hold from Write End
0
—
0
—
0
—
0
—
ns
tHZWE  WE LOW to High-Z Output
—
10
—
15
—
20
—
25
ns
tLZWE  WE HIGH to Low-Z Output
3
—
5
—
5
—
5
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in .igure 1a.
2. Tested with the load in .igure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
DATA UNDEFINED
t WC
VALID ADDRESS
t SCE
t PWE1
t PWE2
t AW
t HA
HIGH-Z
t HD
t SA
t HZWE
ADDRESS
CE
WE
DOUT
DIN
DATAIN VALID
t LZWE
t SD
AC WAVE.ORMS
WRITE CYCLE NO. 1 (9-
9-
9-
9-
9- Controlled)(1,2)



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