LP3220S-00

Jun.-2017

www.lowpowersemi.com

Page 9 of 10

Preliminary Datasheet

LP3220S

Layout Guidance

When laying out the PC board, the following layout guideline

should be followed to ensure proper operation of the

LP3220S:

1. The power traces, including the GND trace, the LX trace

and the IN trace should be kept short, direct and wide to allow

large current flow. The L connection to the LX pins should be

as short as possible. Use several VIA pads when routing

between layers.

2. The feedback trace or OUT pin should be separate from

any power trace and connect as closely as possible to the

load point. Sensing along a high-current load trace will

degrade DC load regulation. If external feedback resistors are

used, they should be placed as closely as possible to the FB

pin to minimize the length of the high impedance feedback

trace.

possible to VIN and GND to get good power filtering.

4. Keep the switching node, LX away from the sensitive FB

node.

closely as possible. The connection of L to the LX pin should

be as short as possible and there should not be any signal

lines under the inductor.

6. The resistance of the trace from the load return to GND

should be kept to a minimum. This will help to minimize any

error in DC regulation due to differences in the potential of the

internal signal ground and the power ground.