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PS9702B Datenblatt(PDF) 5 Page - List of Unclassifed Manufacturers

Teilenummer PS9702B
Bauteilbeschribung  6Ch, 24bit, 192kHz Digital Audio Processor for Full Digital Amplifier
PDF  41 Pages
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PULSUS
PS9702B
Copyright © 2000-2003, Pulsus Technologies Inc.
5
2003 REV1.2
Name
Pin NO.
Type
Description
SLRCK[0:2]
19, 23, 28
I/O
PCM Word clock (left-right clock) input/output of sub-channel
audio.
SSDIN[0:2]
17, 21, 26
I
PCM serial data input of sub-channel audio.
This sub-channel data can be treated as three two-channel
audio or one six-channel audio. When it is used for six-channel
audio, user can select the bit clock and word clock from
SBCK[0:2] and SLRCK[0:2].
MCLK
38
O
Main clock for external A/DC or D/AC.
Clock frequency is 12.288MHz (fixed).
MIC_BCK
35
O
PCM bit clock output of external MIC.
Bit clock frequency is 3.072MHz (48KHz x 64, fixed)
MIC_LRCK
36
O
PCM Word clock (left-right clock) output of external MIC.
Word clock rate is 48KHz (fixed).
MIC_SDIN
34
I
PCM serial data input of external MIC.
Schmitt-Trigger input.
REC_SDO
39
O
PCM serial data output of record-out.
This signal is synchronized to MIC_BCK and MIC_LRCK.
PWM Audio Output
PWM_CH1+
53
O
Positive PWM output of channel 1.
(default setting : front left channel)
PWM_CH1-
54
O
Negative PWM output of channel 1.
PWM_CH2+
56
O
Positive PWM output of channel 2.
(default setting : front right channel)
PWM_CH2-
57
O
Negative PWM output of channel 2.
PWM_CH3+
60
O
Positive PWM output of channel 3.
(default setting : rear left channel)
PWM_CH3-
61
O
Negative PWM output of channel 3.
PWM_CH4+
63
O
Positive PWM output of channel 4.
(default setting : rear right channel)
PWM_CH4-
64
O
Negative PWM output of channel 4.
PWM_CH5+
67
O
Positive PWM output of channel 5.
(default setting : center channel)
PWM_CH5-
68
O
Negative PWM output of channel 5.
PWM_CH6+
70
O
Positive PWM output of channel 6.
(default setting: sub-woofer channel)
PWM_CH6-
71
O
Negative PWM output of channel 6.
REC_PWM_R+
44
O
Positive PWM output of Record-out left channel.
REC_PWM_R-
45
O
Negative PWM output of Record-out left channel.
REC_PWM_L+
48
O
Positive PWM output of Record-out right channel.
REC_PWM_L-
49
O
Negative PWM output of Record-out right channel.
System Control Interface
SPI/I2C
83
I
Host interface mode (SPI or I2C) selector.
Assert ‘HIGH’ for SPI mode. De-assert ‘LOW’ for I2C mode.
Internal pull-down resistor.
SO/SDA
79
I/O
SO for SPI mode or SDA for I2C mode.
SCK/SCL
80
I
SCK for SPI mode or SCL for I2C mode.
Schmitt-Trigger input.



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