MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP

MP8764 Rev. 1.2

www.MonolithicPower.com

13

6/21/2016

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As the output current increases from the light

load condition, the time period within which the

current modulator regulates becomes shorter.

The HS-FET is turned ON more frequently.

Hence,

the

switching

frequency

increases

correspondingly. The output current reaches the

critical level when the current modulator time is

zero. The critical level of the output current is

determined as follows:

IN

SW

OUT

OUT

IN

OUT

V

F

L

2

V

)

V

V

(

I

×

×

×

×

−

=

(2)

It turns into PWM mode once the output current

exceeds the critical level. After that, the switching

frequency stays fairly constant over the output

current range.

Switching Frequency

The selection of switching frequency is a tradeoff

between efficiency and component size. Low

frequency operation

increases

efficiency by

reducing MOSFET switching losses, but requires

larger inductance and capacitance to maintain

low output voltage ripple.

For MP8764

， the on time can be set using

FREQ pin, then the frequency is set in steady

state operation at CCM mode.

Adaptive constant-on-time (COT) control is used

in MP8764 and there is no dedicated oscillator in

the IC. Connect FREQ pin to IN pin through

forwarded to the one-shot on-time timer through

the

resistor

operation at CCM, the duty ratio is kept as

constant over the input voltage range. The

switching frequency can be set as follows:

)

(

)

(

)

(

4

.

0

)

(

)

(

1

.

6

10

)

(

6

ns

T

V

V

V

V

V

V

k

R

kHz

F

DELAY

OUT

IN

IN

FREQ

SW

+

×

−

Ω

×

=

(3)

5ns. After adding load, the frequency may be

affected a little because power MOSFET voltage

drop will affect the duty cycle.

Generally, the MP8764 is set for 200kHz to

1MHz application. It is optimized to operate at

high switching frequency with high efficiency.

High switching frequency makes it possible to

utilize small sized LC filter components to save

system PCB space.

Jitter and FB Ramp Slope

Figure 4 and Figure 5 show jitter occurring in

both PWM mode and skip mode. When there is

HS-FET deviates from its intended location and

produces jitter. It is necessary to understand that

there is a relationship between a system’s

ripple

dominates

in

noise

immunity.

The

noise immunity directly.

Figure 4—Jitter in PWM Mode

Figure 5—Jitter in Skip Mode

Ramp with Large ESR Capacitor

In the case of POSCAP or other types of

capacitor with lager ESR is applied as output

capacitor, the ESR ripple dominates the output

ripple, and the slope on the FB is quite ESR

related. Figure 6 shows an equivalent circuit in

PWM mode with the HS-FET off and without an

external

ramp

circuit.

Turn

to

application