IC41C16256

IC41LV16256

4

Integrated Circuit Solution Inc.

DR018-0C 04/23/2004

TRUTH TABLE

Function

RAS

RAS

RAS

RAS

RAS

LCAS

LCAS

LCAS

LCAS

LCAS UCAS

UCAS

UCAS

UCAS

UCAS

WE

WE

WE

WE

WE

OE

OE

OE

OE

OE

I/O

Standby

H

H

H

X

X

X

High-Z

Read: Word

L

L

L

H

L

ROW/COL

Read: Lower Byte

L

L

H

H

L

ROW/COL

Upper Byte, High-Z

Read: Upper Byte

L

H

L

H

L

ROW/COL

Lower Byte, High-Z

Write: Word (Early Write)

L

L

L

L

X

ROW/COL

Write: Lower Byte (Early Write)

L

L

H

L

X

ROW/COL

Upper Byte, High-Z

Write: Upper Byte (Early Write)

L

H

L

L

X

ROW/COL

Lower Byte, High-Z

LL

L

H

→LL→H

ROW/COL

1st Cycle:

L

H

→LH→L

H

L

ROW/COL

2nd Cycle:

L

H

→LH→L

H

L

NA/COL

Any Cycle:

L

L

→HL→H

H

L

NA/NA

1st Cycle:

L

H

→LH→L

L

X

ROW/COL

2nd Cycle:

L

H

→LH→L

L

X

NA/COL

EDO Page-Mode

1st Cycle:

L

H

→LH→LH→LL→H

ROW/COL

2nd Cycle:

L

H

→LH→LH→LL→H

NA/COL

Read L

→H→L

L

L

H

L

ROW/COL

Write L

→H→L

L

L

L

X

ROW/COL

RAS-Only Refresh

L

H

H

X

X

ROW/NA

High-Z

H

→L

L

L

X

X

X

High-Z

Notes:

1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).

2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).

3. At least one of the two CAS signals must be active (LCAS or UCAS).