MPC755 datasheet(21/56 Pages) MOTOROLA

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MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 8 shows the L2 bus input timing diagrams for the MPC755.

Figure 8. L2 Bus Input Timing Diagrams

Figure 9 shows the L2 bus output timing diagrams for the MPC755.

Figure 9. L2 Bus Output Timing Diagrams

Figure 10 provides the AC test load for L2 interface of the MPC755.

Figure 10. AC Test Load for the L2 Interface

4.2.5

IEEE 1149.1 AC Timing Specifications

Table 13 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 12 through Figure 15.

Table 13. JTAG AC Timing Specifications (Independent of SYSCLK) 1

At recommended operating conditions (see Table 3)

Parameter

Symbol

Min

Max

Unit

Notes

TCK frequency of operation

fTCLK

016

MHz

TCK cycle time

tTCLK

62.5

—

TCK clock pulse width measured at 1.4 V

tJHJL

—

TCK rise and fall times

tJR, tJF

L2SYNC_IN

L2 Data and Data

VM = Midpoint Voltage (L2OVDD/2)

tDVL2CH

tDXL2CH

tL2CR

tL2CF

Parity Inputs

L2SYNC_IN

All Outputs

VM = Midpoint Voltage (L2OVDD/2)

tL2CHOV

tL2CHOX

L2DATA BUS

tL2CHOZ

Output

Z0 = 50 Ω

L2OVDD/2

RL = 50 Ω

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