Silan

Semiconductors

SC8521

HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

REV: 1.3

2002.03.01

5

generated code temporarily (select different bank) to obtain multi-function keys. With this option the jumper wires

or switch must be connected between sense line SN0 and one of the drivelines DR0 to DR6 or ground. This

means that SN0 cannot be used to connect keys and the maximum number of keys will be 49 keys for a 20-pin

package.

It is not possible to use a combination of jumper wires and selection keys for bank selection in one unit. The

output of the ROM is loaded into a shift register that provides the input bits for the pulse generator. This pulse

generator drives the output pin.

2. Timing generator

A schematic diagram of the timing generator is illustrated the oscillator frequency is 432KHz. The timing

generator is stopped when no key is activated and started again when a key is pressed.

The output of the oscillator (CLK1) is divided by 12 for 432KHz. Selection is achieved using a mask option. The

output of the divider is CLK2 which is used for clocking of the control timer. The frequency of CLK2 is 36 KHz and

the inverse is used to generate the output pulses in the subcarrier frequency. By mask option the duty factor can

be chosen to be 25% or 33%.

The control timer has a length of 4096 subcarrier (pulse) periods. This is equal to the transmission repletion time.

A bit time is equal to 64 pulses and the repetition time is 64 bit times. The control timer provides the timing of the

key scanning, the ROM access and the code transmission. When the control timer has arrived at a certain state

and no key has been pressed for at least 28 ms, a stop signal will be generated which will stop the oscillator. All

drivelines will then be set to logic 0. As soon as a key is pressed one of the sense lines will become logic 0. This

will generate a start signal, which will restart the oscillator.

OSCILLATOR

DIVIDE BY 12

CONTROL

TIMER

DIVIDE-BY-4096

C0

C11

pulse

R

SQ

Q

CLR

432kHz

no key

end control

start input

STOP

CLK1

432 kHz

INV

CLK

CLK2

Timer schematic diagram