6

LP5018, LP5024

SLVSEB8 – MARCH 2018

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Copyright © 2018, Texas Instruments Incorporated

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

Voltage on ADDRx, EN, IREF, OUTx, SCL, SDA, VCC

–0.3

6

V

Voltage on VCAP

–0.3

2

V

Continuous power dissipation

Internally limited

–40

125

°C

–65

150

°C

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1500

V may actually have higher performance.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V

may actually have higher performance.

7.2 ESD Ratings

VALUE

UNIT

Electrostatic discharge

±1500

V

Charged-device model (CDM), per JEDEC specification JESD22-

±500

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

MAX

UNIT

Input voltage on VCC

2.7

5.5

V

Voltage on OUTx

0

5.5

V

Voltage on ADDRx, EN, SDA, SCL

0

5.5

V

–40

85

°C

(1)

For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

7.4 Thermal Information

LP5018 or LP5024

UNIT

RSM (QFN)

32 PINS

Junction-to-ambient thermal resistance

36.4

°C/W

Junction-to-case (top) thermal resistance

34.8

°C/W

Junction-to-board thermal resistance

15.9

°C/W

Junction-to-top characterization parameter

0.9

°C/W

Junction-to-board characterization parameter

16

°C/W

Junction-to-case (bottom) thermal resistance

6.3

°C/W